Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with MTJ technology, is a major emerging technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, Flash, etc. A MRAM device is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction perpendicular to the first conductive lines, and an MTJ element interposed between a first conductive line and a second conductive line at each crossover location. A first conductive line may be a word line while a second conductive line is a bit line or vice versa. Alternatively, a first conductive line may be a bottom electrode that is a sectioned line while a second conductive line is a bit line (or word line). There are typically other devices including transistors and diodes below the array of first conductive lines as well as peripheral circuits used to select certain MRAM cells within the MRAM array for read or write operations.
An MTJ element may be based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. An MTJ stack of layers may be formed in a so-called bottom spin valve configuration by sequentially depositing a seed layer, an anti-ferromagnetic (AFM) pinning layer, a ferromagnetic “pinned” layer, a thin tunnel barrier layer, a ferromagnetic “free” layer, and a capping layer on a substrate.
The AFM layer holds the magnetic moment of the pinned layer in a fixed direction. The pinned layer has a magnetic moment that is fixed in the “y” direction, for example, by exchange coupling with the adjacent AFM layer. The free layer has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer and is preferably made of NiFe because of its reproducible and reliable switching characteristics as demonstrated by a low switching field (Hc) and switching field uniformity (σHc). The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may change in response to external magnetic fields and it is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. When a sense current is passed from the top electrode to the bottom electrode in a direction perpendicular to the MTJ layers, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“1” memory state) and a higher resistance is noted when they are in an anti-parallel state or “0” memory state.
In a read operation, the information stored in a MRAM cell is read by sensing the magnetic state (resistance level) of the MTJ element through a sense current flowing top to bottom through the cell in a current perpendicular to plane (CPP) configuration. During a write operation, information is written to the MRAM cell by changing the magnetic state in the free layer to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents in two crossing conductive lines, either above or below the MTJ element. In certain MRAM architectures, the top electrode or the bottom electrode participates in both read and write operations. An alternative MRAM technology is referred to as spin-transfer torque (STT) MRAM. Unlike conventional MRAM that requires a separate word line in addition to a BIT line to switch the magnetization direction of a free layer in a MTJ, STT-MRAM relies only on a current passing through the MTJ to rotate the free layer magnetization direction.
Generally, the purpose of a capping layer or top electrode is to protect underlying layers in the MTJ during etching and other process steps and to function as an electrical contact to an overlying conductive line. In the fabrication of MRAM devices, well defined three dimensional nanometer sized features are created by patterning a photoresist or mask layer on a stack of MTJ layers and then transferring the pattern in the mask through multiple layers of magnetic layers using a reactive ion etch (RIE) process. Etching proceeds chemically which involves a surface reaction between gaseous reactants and the material being removed that generates volatile etch products. RIE offers a better approach to etching MTJs compared with conventional ion beam etching (IBE) methods where the material is etched physically through ion bombardment. In IBE, the resulting MTJ profile is highly tapered because the sputtered non-volatile etch products are deposited back onto the MTJ sidewalls so that the width of an uppermost top electrode along an easy axis direction is substantially less than that of a seed layer which contacts a bottom electrode. A tapered profile can not only lead to electrical shorting issues but also limits further reduction of critical dimension (CD) of MRAM devices and makes it nearly impossible to manufacture very high density IC devices such as spin torque MRAM.
In the current MRAM fabrication process, a heavy metal such as Ta is deposited on top of a MTJ stack of layers, and acts both as a hard mask for the etching of the MTJ stack and as an interlayer conduction channel to the top bit line as described in U.S. Pat. No. 7,060,194. The thickness of the heavy metal layer should be sufficient to prevent electrical shorting between the MTJ and overlying bit line. On the other hand, the heavy metal layer should not be too thick since a thicker photoresist mask will be required for pattern transfer and as the photoresist thickness increases there is a greater tendency for the photoresist pattern to collapse which drives more rework and higher cost. Therefore, the heavy metal layer thickness is determined by maintaining a balance between the need for a thicker layer to avoid electrical shorting and a thinner layer to prevent pattern collapse in an overlying photoresist layer.
Selection of an appropriate heavy metal to serve as a hard mask when etching a MTJ stack of layers is also critical. The ideal hard mask material should have a high etch rate selectivity to overlying and underlying layers, and more importantly should not be prone to metal etch residue buildup. Formation and buildup of metal etch residue significantly affects the shape integrity of MTJ structures which in turn affects MRAM device performance. When Ta is selected as the heavy metal hard mask material, it is well known that etching Ta in CF4 plasma with an overlying photoresist mask is highly likely to deposit Ta etch residues on MTJ sidewalls. Consequently, MTJ shape integrity is lost and MRAM device performance suffers. Problems with shape integrity become more challenging as device CD shrinks. FIG. 1 shows a top view of examples of 80 nm×160 nm MTJ elements 10-13 formed on a substrate 8 and that were etched using a Ta hard mask (not shown). MTJs 10-13 are greatly deformed from the oval shape in the mask design used to generate a pattern in a photoresist layer (not shown). There are also defects comprising metal etch residue which are shown as shapes 10a, 12a that are separated from nearby MTJs 10, 12, respectively, and a defect 11a that is attached to a side of MTJ 11. In a manufacturing environment, the MTJ shapes and defects shown in FIG. 1 would be unacceptable and substrate 8 would require rework.
Fabrication of MTJ cell dimensions of about 100 nm or less requires a thin photoresist layer (<3000 Angstroms) to ensure an adequate process latitude when imaging small features on a hard mask that will later be transferred through the hard mask and a MTJ stack of layers. It is well known that an aspect ratio (thickness/width of a pattern feature) of about 3:1 or less is preferred to avoid pattern collapse during image development. However, a thin photoresist layer requires a thin Ta hard mask layer to guarantee that the hard mask pattern will be completely formed before the photoresist etch mask is consumed during the etch transfer step. Unfortunately, a thin Ta hard mask leads to potential issues of electrical shorting as mentioned previously and limits the amount of etch time available to transfer the hard mask pattern through the MTJ stack of layers because the hard mask erodes during the pattern transfer process. Thus, other alternatives besides a simple Ta hard mask are necessary when fabricating MTJ cells having an easy axis or hard axis dimension of about 100 nm or less.
One alternative described in U.S. Pat. No. 7,001,783 is a bilayer hard mask consisting of an upper dielectric layer made of SiO2, silicon nitride, silicon carbide, or the like, and a lower heavy metal layer (Ta) that contacts the free layer in the MTJ stack of layers. A pattern in the dielectric layer is used to pattern the Ta layer. The dielectric layer is removed before a subsequent etch step is performed to transfer the Ta hard mask pattern into an upper magnet. Later, a second composite hard mask is laid down and is involved in patterning a lower magnet in the MTJ. Overall, the entire patterning sequence involves several additional steps than in a single composite hard mask scheme and there is no protection of the Ta hard mask during etching of MTJ layers. Therefore, a new MTJ hard mask design is needed that employs only one composite hard mask wherein a heavy metal layer such as Ta is protected during pattern transfer into the MTJ stack of layers so that shape integrity is not affected by undesirable metal etch residues.
U.S. Pat. No. 6,984,529 describes a patterned hard mask which is oxidized to form an oxide surface before etching the underlying MTJ stack of layers to form a MTJ element.